Resource Library

RTL to Gate Signoff Constraint Development Using Timevision presented by Arm

Video

Timevision Mode Merge Used in Timing ECO Flow presented by Broadcom

Video

Mode Merge

Video  |  Streaming Video

Simplifying mode merge for modern designs

SoC Budgeter

Video  |  Streaming Video

Accurate IO budgets for all blocks in the design

Check SDC

Video  |  Streaming Video

Verifying Clock Groups

SoC Hierarchy

Video  |  Streaming Video

Verifying clock groups between the top level and block level

Taming MMMC Mayhem

Blog

The shrinking of technology nodes has caused an inversion of parasitic concerns where once the cell delay dominated the interconnect delay, now the interconnect delay dominates the cell delay. Likewise, in EDA tools, technology nodes down to submicron had silicon vendors primarily concerned with productivity and runtimes, just to name couple.

Not much change in constraints ... Leads to Thousands of violations

Blog

How often have you come across the scenario where your block or full chip timing is clean or close to clean and then you get constraint drop from constraints owner saying, “not much change in the constraints”? To your surprise after using the new constraints you see thousands of timing violations.

Seemingly Simple Clock Relations Quiz

Blog

Getting clock relationships correct is very important. In order to get the “set_clock_groups” constraints correct the designer must specify the correct clock pair relationship. If the relationship is incorrect it could lead to over pessimism in Crosstalk/SI analysis, or worse, false path between synchronous clocks.

Pitfall of Tcl - Over Reaching Timing Exceptions

Blog

Generating set_false_path and set_multicycle_path timing exceptions can be an arduous task for block owners in an SoC. It requires detail understanding of the design, which usually remains with the RTL designer, and sometimes several STA iterations to reveal timing violations where exceptions may be required.