News & Events


Ausdia Unveils Timevision-HyperBlock at DAC 2024

Revolutionary Constraint Management Technology Addresses AI Chip Design Challenges with 10x Memory Reduction and 20x Performance Boost

NEWS  |  Jun 21st, 2024

Ausdia Introduces Spreadsheet Constraints at the 60th Design Automation Conference

Ausdia, the leading developer of design constraints verification and management solutions, introduced a significant enhancement to its SDC platform at the 60th Design Automation Conference (DAC) 2023.

NEWS  |  Jul 7th, 2023

InSemi & Ausdia - Two Tech Leaders Partner for Semiconductor Design Excellence

Ausdia's Timevision is the leader in timing constraints development, verification and management - complementing implementation and timing signoff flows across the silicon design marketplace. Customers often request design consulting services to complete their constraints development and timing closure tasks on their designs. Ausdia is delighted to partner with InSemi to help fulfill this need while staying focused on delivering its leading EDA products to mutual customers.

NEWS  |  Nov 24th, 2022

Deep Chip - Ausdia Timevision vs Spyglass, Fishtail and Excellicon for SDC

7nm closure is going to be a real bear! read more of the different between Timevision and competitors tools

NEWS  |  May 29th, 2018

EDACafe: Video interview at DAC with CEO, Sam Appleton

Learn about Ausdia and new Budgeter module @ DAC 2018.

NEWS  |  Jul 27th, 2018

Ausdia Theater Presentations at DAC

EVENTS  |  May 19th, 2018

Analyzer merges constraints for multiple timing modes

Tech Design Forum: Analyzer merges constraints for multiple timing modes

NEWS  |  Jun 7th, 2016

Ausdia Introduces Hierarchical Budget Analysis and Asynchronous Glitch Detection Add-ons to Timevision

Add-ons generate, verify and refine hierarchical timing budgets; screen and locate “glitchy” logic; and reduce analysis noise

NEWS  |  Jun 4th, 2015

BRCM Engineering evaluates Ausdia

NEWS  |  May 22nd, 2015

Timing Closure Experts Launch New Company, Announce Proven Timing Constraints Platform

Ausdia helps SoC and IC developers make massive productivity gains across the design flow

NEWS  |  Jun 12th, 2013