AUSDIA is now part of Cadence
AUSDIA is now part of Cadence
The premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits.
Learn more about DVCon India 2025 and register to attend.
Timing constraints continue to be a major challenge to SoC design closure, even with more tools & methodologies being created to address piecemeal parts of the problem. This talk will focus on the unique challenge presented by timing constraints - how the design team establishes a single "source-of-truth" to drive signoff and retains the golden source and extends it as a root-of-trust across the design flow and into SoC integration.
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