AUSDIA is now part of Cadence
AUSDIA is now part of Cadence
SUNNYVALE, Calif. – September 17, 2024 – Ausdia, the leading developer of design constraints verification and management solutions will showcase its recently announced Timevision-HB, the revolutionary constraint management technology that addresses AI chip design challenges with 10x memory reduction and 20x performance boost at DVCon India 2024, being held September 18 – 19, 2024 in Bangalore, India.
Timevision-HB addresses the growing challenges faced by design teams in the AI era, including design sizes that push reticle limits, integration issues with large amounts of third-party IP and short time-to-market windows. The innovative HyperBlock technology uses an advanced abstraction system to create a minimal representation of SoC design blocks while retaining all critical information necessary for SDC constraint loading.
Timevision-HB was recently announced at the 61st DAC, Chips to Systems Conference 2024.
Timevision™ is a comprehensive timing constraints development, verification, and management solution that complements all implementation and timing signoff flows. It has the capacity to handle over 1 billion cells and thousands of clocks. Timevision integrates with all aspects of the design flow and is used before synthesis, before DFT insertion, before place and route, and when signoff timing is being run.
DVCon India, is the yearly regional conference in India, of DVCon. DVCon is the premier conference on the application of languages, tools and methodologies for the design and verification of electronic systems and integrated circuits. The focus of the conference is on the usage of specialized design and verification languages.
When: September 18 – 19, 2024
Where: Radisson Blu, Marathahalli, Bangalore, India (Booth 18)
Registration: https://dvcon-india.org/registration/
