Cadence Design Systems
AUSDIA is now part of Cadence
Cadence Design Systems
AUSDIA is now part of Cadence

News & Events

< Back to News & Events

 

Can EDA Cut Through the Timing Complexity in Big AI Chips?

Aug 8th, 2024

To remain relevant in the AI era, semiconductor firms and even many systems companies are rolling out a new class of ultra-large systems-on-chips (SoCs), using advanced process nodes to cram tens of billions of transistors on slabs of silicon pushing the reticle limits of modern chips. These chips contain more than a billion standard cells, growing amounts of third-party IP, and up to thousands of clocks to keep everything coordinated. All of these factors are causing complexity to explode at a time when time-to-market is shrinking.

As the scaling of transistors slows down, it’s also becoming standard practice to bind heterogeneous dies or chiplets in 2.5D and 3D configurations, squeezing even more square millimeters of silicon into a package. 

CONTINUE STORY AT ELECTRONIC NEWS

TOP