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Ausdia Introduces Timevision NFormal at the 59th Design Automation Conference

Jul 11th, 2022

DESIGN AUTOMATION CONFERENCE, SAN FRANCISCO – July 11, 2022 – Ausdia, the leading developer of design constraints verification and management solutions, introduced a major enhancement to its SDC formal platform at the 59th Design Automation Conference (DAC) 2022.

TimevisionTM NFormal features a new frontend for advanced proof grouping, an adaptive logic model that iteratively generates the most accurate proof states, and additional prover engines for SDC verification that transparently adapt to the design without sacrificing proof quality.
“We used Ausdia’s Timevision constraints and exception verification platform on a range of IP blocks in a current design implementation, and addressed multiple legitimate issues found automatically by the tool”, said Namit Varma, Sr. Director, India Technology Center at Achronix. “These included a number of incorrect false & multicycle paths flagged by Timevision’s formal verification engine. Correcting these issues early led to us having much higher confidence in the quality of the timing constraints, given the rigorous analysis performed by Timevision.”

Timevision is a comprehensive timing constraints development, verification and management solution that complements all implementation and timing signoff flows. It has the capacity to handle over 1 billion cells and thousands of clocks. Timevision integrates with all aspects of the design flow and is used before synthesis, before DFT insertion, before place and route, and when signoff timing is being run. Timevision helps designers create good SDC constraints and is a verification platform for existing timing constraints.

Ausdia is highlighting the Timevision platform in booth # 2310 at the Design Automation Conference (DAC) being held at Moscone West in San Francisco, CA from July 11 - 13, 2022.

Timevision NFormal is scheduled for general availability in Q4 2022.

About Ausdia
Ausdia delivers standout timing constraint development, verification, and management solutions that complement all implementation and timing signoff flows. The company’s groundbreaking methodology and products give system-on-chip (SoC) and integrated circuit (IC) developers a new way to work, enabling massive productivity gains throughout the design flow. Founded in 2006, the privately held company is headquartered in Sunnyvale, California.

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