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Topic: SDC Checks


Taming MMMC Mayhem

Apr 28th, 2020   |   Hollis, Robertson

The shrinking of technology nodes has caused an inversion of parasitic concerns where once the cell delay dominated the interconnect delay, now the interconnect delay dominates the cell delay.  Likewise, in EDA tools, technology nodes down to submicron had silicon vendors primarily concerned with productivity and runtimes, just to name couple.  Now silicon vendor concerns are predictability, turnaround time (TAT), power performance area (PPA), return on investment (ROI), and server cost, to name a few.  Every EDA tool must contribute positively to some of these concerns to be a viable solution.  The anonymous user “Jumanji, the Next Level” in DeepChip post “ESNUG 588 Item 13” made it very clear several of these were evaluation criteria for their design flow decision. As “Jumanji, the Next Level” pointed out vendors no longer have the luxury of using just one technology node for a year or two because different chips in different markets require different technology nodes to keep up with feature, area, and performance enhancements.

As block size increase along with chip size EDA tool absolutely must scale.  It is counterproductive to have a user black box various module in order to run STA or CDC at block, chiplet or full chip level.

“Jumanji, the Next Level” emphasized their signoff goal is to increase the number of signoff corners from 84 to 137.  Imagine a SoC with 150 blocks running 137 corners on, say, 7 modes. Forget about full chip for now. That’s 150 X 137 X 7 = 143,850 different STA runs, excluding hold time STA runs. Now add to that multiple chips going through the design flow in parallel.  That is an enormous number of compute servers. One can easily imagine if any step in the process is manual how risky and time consuming it would be.


Figure 1 shows a simple example of the “single mode” STA run diagram.


I will address scalability in another blog, for now we focus on all those STA runs.  Is there any way to reduce them at all?  Well, sure, the number of corners could be reduced.  However, if the fab requires all 137 corners then this is not an option.  The number of blocks could be reduced but then the STA and PnR tool must have larger capacity.  This would impact TAT.  Another option is to reduce the number of modes.  There are several EDA vendors claiming they can merge all the modes, but to be honest, we have not seen that yet.

This is where Ausdia’s merge mode feature stands alone.  Ausdia’s merge mode feature is a true “many” to “single” merge mode feature.  While we cannot change the number of corners, or the number of blocks, Ausdia can change the number of modes.  Now the SoC team would be looking at 150 X 137 X 1 = 20,550 STA runs, not including hold time runs.

Figure 2 shows a simple example of the “merged mode” STA run diagram.


Another significant benefit is that this same merged SDC could be used in PnR.  This would eliminate the ping-ponging of fixing one mode and messing up another.  Every mode is presented simultaneously to the PnR tool, it is only the corners that change.  The block owners would only need to run all “single modes” and all corners once for golden timing signoff.

“Jumanji, the Next Level”, I hope you consider adding Ausdia merge mode to your flow, looks like things will only get worse.


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