Timevision™ Modules

A solution for constraints development and verification, allowing
system-on-chip (SoC) and integrated circuit (IC) developers to
make massive productivity gains across the design flow.

SOC Budgeter Check SDC Formal SDC SoC Hierarchy Mode-Merge Extracted Timing Model (ETM) Diff SDC Multi-Mode Coverage Design-For-Test (DFT) Clock Domain Crossing (CDC) Glitch

EXTRACTED TIMING MODEL (ETM)

ETMs are used extensively in modern SoC designs to speed up the turn-around time of timing analysis. By abstracting away, the contents of the block, analysis time is dramatically reduced. This allows designers an accurate view of full-chip timing without the excessive run times associated with flat analysis.

However, using ETMs requires several steps. Step one, the designer needs to verify the results matching the netlist and SDC. Step two, generate a new full-chip SDC with the block(s) replaced with ETM models. Step three, verify the ETM-based full-chip SDC file matches the flat view. With Timevision ETM these steps are performed automatically, allowing the use of ETM-based timing flows without the manual effort necessary to support them.

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