Cadence Design Systems
AUSDIA is now part of Cadence
Cadence Design Systems
AUSDIA is now part of Cadence

Timevision™ Modules

A solution for constraints development and verification, allowing
system-on-chip (SoC) and integrated circuit (IC) developers to
make massive productivity gains across the design flow.

SOC Budgeter Check SDC Formal SDC SoC Hierarchy Mode-Merge Extracted Timing Model (ETM) Diff SDC Multi-Mode Coverage Design-For-Test (DFT) Clock Domain Crossing (CDC) Glitch

Clock Domain Crossing (CDC)

With designs having upwards of 1,000 clocks to verify as part of a design signoff flow, CDC is a critical check in today’s complex SoC designs. Timevision CDC directly utilizes SDC timing constraints to verify clock domain crossings with a robust suite of checks, including synchronization and handshakes, FIFOs, resets and synchronized structure checks. Working with either RTL or gate-level netlists at up to 1 billion instances, Timevision CDC can be used all the way to gate-level signoff for CDC checking.

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