Timevision Modules

A solution for constraints development and verification, allowing
system-on-chip (SoC) and integrated circuit (IC) developers to
make massive productivity gains across the design flow.

Formal SDC

Timing Exceptions (multi-cycle paths and false paths) are used extensively to relax timing in critical or known areas of a design. However, these exceptions must be verified in order to provide confidence the design will work once fabricated.

Timevision Formal SDC uses static formal verification techniques to formally check timing exceptions, and provides a full suite of features to generate SVA (System Verilog Assertions) to check and debug timing exceptions in functional simulation engines.


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