Timevision™ Modules

A solution for constraints development and verification, allowing
system-on-chip (SoC) and integrated circuit (IC) developers to
make massive productivity gains across the design flow.

SOC Budgeter Check SDC Formal SDC SoC Hierarchy Mode-Merge Extracted Timing Model (ETM) Diff SDC Multi-Mode Coverage Design-For-Test (DFT) Clock Domain Crossing (CDC) Glitch

MODE-MERGE

Constraints on functionality, power and reuse often compel designers to make their RTL have multiple operating modes, controllable by constant settings in firmware or clock controllers. Back-end engineers need to design timing constraints that cover all possible operating modes of the RTL. 

This is a technically challenging task, not including the need to verify the resulting SDC.  Timevision Mode-Merge takes an arbitrary number of SDC files, representing multiple operating modes, and produces a single SDC file that covers all modes in the one run – reducing the number of back-end licenses needed to close the block, while ensuring all timing paths are covered in the single merged mode.

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Timevision Mode Merge Used in Timing ECO Flow presented by Broadcom

Mode Merge

Simplifying mode merge for modern designs

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