Timevision Platform

A powerful and trusted design constraint development and verification
platform that allows system-on-chip (SoC) developers
to make massive productivity gains across the design flow.

TimevisionTM: Design Constraint Technology

Market situation & the need for design constraint technology:

Silicon design is becoming vastly more complicated and costly, and harder to design and verify. Today’s SoCs drive this exploding complexity – thanks to raw design size, increasing use of IP blocks, advanced technology node, number of clocks and clocked domains, and complexity of constraints to close timing across all combinations of corners and modes. There is a demand for a comprehensive product to generate and validate design constraints that correlate with static timing analysis engines to ensure design correctness.

The huge cost of an error in constraints, clocking or timing often forces design teams to adopt a minimization strategy – designing a completely minimal, safe set of timing constraints that are the least prone to error. Experienced leaders in the silicon design field recognize this as a complex, multi-faceted problem that requires a variety of capabilities and techniques to attack. Simple structural or semantic tools and approaches will only catch simple problems while emitting copious numbers of false-positive errors requiring designer review. The solution should aid in the goal of helping the design team create design constraints that cover the requirements of the design, allowing it to meet its power, performance and area goals while minimizing the risk of a respin due to a clocking or timing issue.

TimevisionTM is a comprehensive platform solution to generate and validate timing constraints that correlate with static timing analysis engines to ensure design correctness. Using multi-core software architecture, patented analysis algorithms, and innovative formal verification technology, the founders of Ausdia created Timevision to handle large, complex SoC designs–especially above 100+ million instances. 


Resource Available

RTL to Gate Signoff Constraint Development Using Timevision presented by Arm

Timevision Mode Merge Used in Timing ECO Flow presented by Broadcom

Mode Merge

Simplifying mode merge for modern designs

SoC Budgeter

Accurate IO budgets for all blocks in the design

Check SDC

Verifying Clock Groups

SoC Hierarchy

Verifying clock groups between the top level and block level