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Despite the proliferation of sophisticated timing-driven place-route-optimization tools, timing closure remains a difficult, painful and unpredictable precess for a large number of design teams. It can take weeks to months for a stable, clean design to be closed and moved through to the tapeout step – even with talented, experienced and committed engineers.
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Ausdia is in the alpha - development phase of a revolutionary solution to the timing convergence problem that : |
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Leverages your existing investments in tools from the Big-3 EDA vendors |
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Retains your investments in methodology, flows and expertise |
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Is designed in harmony with expert chip designers – those who truly understand all the facets of the problem and how it can be solveds |
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Parties interested in being development partners should contact us at partners@ausdia.com to arrange a confidential briefing. |
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Solution Packs |
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Ausdia has packaged some common requirements into “solution packs” – a process and methodology for solving particular problems in ASIC/COT closure. |
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Block-level timing closure in challenging designs – BlockClose Pack |
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FullChip STA environment for a clean-slate design – FullChip Pack |
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Analysis/closure of timing on an interface “X” – Interface Pack |
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Timing Comparison between two design flow stages – Compare Pack |
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These help us hit the ground running immediately, and help you understand how the problem will be resolved in concert with your team. Solutions packs comprise : |
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A predefined, tested process for quickly understanding problem scope and expected complexity, and providing a well-defined path to the end goal |
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IP (scripts and Ausdia-developed tools) to enhance the TAT and complexity that can be handled
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Top-tier service delivery to get the job done |
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