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Ausdia can provide a range of services for the implementation of ASIC/COT designs, from RTL design through to the full breadth of the RTL-to-GDSII process.
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Timing Closure Expertise |
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Our background is in timing closure of complex SOC and ASIC designs. We can deliver |
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Post-synthesis feasibility and full-chip timing analysis |
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Interface timing to soft/hard IP components and constraint validation, for example |
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DDR/SDR interfaces |
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On-chip eDRAM designs |
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SERDES/PHY interface |
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Video/Audio interfaces |
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Hard-IP interfaces |
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Serial Interfaces |
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On-chip variation analysis/closure, with process & parasitic corner variations |
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Custom physical/timing constraints for closure, combined with full-chip constraints for analysis |
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Resolve IP, constraint and tool issues that block your path to closure |
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Tools |
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Ausdia has developed proprietary tools and techniques for automating, augmenting and accelerating the timing analysis and closure flow. We do not disrupt your existing design flows, methodology, scripts or methods. Rather, we integrate seamlessly into your existing flow and toolset to help you resolve your most vexing challenges in timing closure. Ausdia's tools have been tested with :-
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Synopsys Astro and PrimeTime |
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Cadence SOC Encounter |
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Magma Blast Fusion and Quartz Time |
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Sequence Cool Time |
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With over 20 years and 15 tapeouts of combined experience in hands-on ASIC development, Ausdia has the breadth and depth to tackle any problem in your design.
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