Constraints Design & Verification
Timevision is a solution for constraints development and verification. It's suited for team members at the RTL, STA/synthesis, and implementation stages.

A sample use-model is
Alignment to STA
Constraint tools are used to verify and generate timing constraints to be "consumed" by implementation and signoff STA solutions. Therefore, it's imperative that constraint tools understand timing in the same way as STA solutions - in other words, that they have an internal timing graph that mirrors, as closely as possible, the view of an STA tool. Without this, it's pointless to create or verify constraints for consumption by STA - if they don't agree, how can you converge? This then becomes a potent combination - Timevision constraints, and your implementation and signoff STA - reducing designer "frustration-by-iteration" and complementing existing flows.
Interactive Debug
One standout feature of Timevision is debug - once a failure or a potential constraint error is located, how easy is it to debug? Timevision includes full SDC backtrack and design interactive analysis, and upcoming GUI features will enhance this even further.
We architected this solution for insane performance and capacity. We support designs up to 200M instances, and constraint verification even on a large design is typically less than one hour. Timevision uses modern multicore software to enhance performance and scalability, with virtually linear speedups across most computationally intensive tasks.

For example, a 5M instance, 120 clock design runtime on a 4-core server is around 45 minutes.
Ultimately, any constraint analysis solution must have superior runtimes compared to an STA tool - engineers would rather load designs in a "true" timing environment and debug there, rather than wait for another tool to load and run. Constraint analysis must offer significantly faster TAT and incremental update compared to STA tools on the same design.

Timevision runtimes are 5 to 10x faster than STA tools for constraint checking, and take full advantage of modern multicore machines.

Formal Technology
The final piece in a constraints solution is the underlying Formal Technology for clock analysis, exception verification and generation and clock domain crossing verification. Timevision includes a complete formal verification engine, designed using the latest techniques in symbolic and Boolean analysis, that delivers on the promise of Fullchip SoC formal technology. Timevisionís formal technology includes a exception engine tuned to the false path/multicycle path problem, and offers massive capacity using a combination of threads and advanced algorithms.