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TIMEVISION - CONSTRAINT DEVELOPMENT |
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TimeVision has a set of features for deriving and verifying, either incrementally or from scratch, a set of
timing constraints for a block. These are focused into the areas of clock source identification and
validation, interclock exceptions, IO constraints and hierarchical constraint verification. Additionally, our
Constraint Management feature ensures that a set of “good” constraints stays good throughout the
design process.
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Clock Identification |
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Identify potential clock sources for all registers with no clock constraint |
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Identify potential missing clock sources for any register, even for those with a clock constraint |
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Validate the consistency of clock definitions against design structure |
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Interclock Exceptions |
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Automatically generate interclock false_paths (either incremental or from scratch) |
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Verify existing interclock exceptions |
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Justify/debug interclock logic |
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Automatically derive set_clock_group for signoff and validate against set_false_path exception
set |
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Transparent handling of virtual clocks |
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IO Constraints |
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Identify missing, incomplete or incorrect IO constraints |
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Automatically generate IO constraints for all ports |
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Categorize IO ports and constraints for better visibility |
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Transparent handling of virtual clocks |
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Clock Logic Analysis |
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Automatically generate clock tree schematics for LRDs, driving CTS and design reviews |
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Analyze clock tree logic to drive complex CTS implementations |
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Hierarchical Constraints |
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Validate fullchip constraints against block-level constraints |
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Derive block SDC from toplevel constraints (top-down) |
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Extract and integrate blocklevel constraints to toplevel (bottom-up), including incremental
changes |
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Hierarchical Analysis |
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Generate block connectivity matricies to drive floorplan and pin assignments |
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Hierarchical lint for unconnected, floating or tied ports to assist in cleanup and constraint
development |
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Hierarchical clock analysis to drive toplevel CTS implementation, including auto-generated
schematics |
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Source-synchronous interface identification and management |
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