Ausdia gives design engineers a powerful, trusted, integrated platform to solve timing generation and verification issues at any level of design (RTL to gate-level). Shrinking design time from months to days.
Ausdia Inc. is an experienced, trusted technology company solving design's toughest problems and transforming SoC design. The company is focused on delivering proven design constraint development and verification solutions that complement all implementation and timing signoff flows.
Ausdia's groundbreaking approach represents a new way for STA developers and users to enable massive productivity gains across the design flow resulting in shrinking design time which ultimately leads to a significant saving in design costs. Founded in 2006, Ausdia has a combined experience of over 60 years in EDA development, chip engineering and methodology.
Ausdia's flagship platform – TimevisionTM – allows STA engineers to dramatically increase their productivity by operating as constraint synthesizers, rather than line-by-line writers and debuggers. Timevision integrates a variety of formal, structural and simulation-based technologies to aid STA engineers in the quick and confident development of constraints from high-level data.
Timevision brings this same capability to RTL designers, who are often under extreme pressure to be involved with timing closure (but lack the time available to dive into gate-level issues). The platform also assists implementation engineers in trying to make sense of constraints and how best to implement their designs (but lack the detailed knowledge of the design).
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