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Ausdia is dedicated to solving the toughest problems in timing analysis and closure.
Our solutions bring control and insight to the timing closure process, without compromising flexibility.
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Ausdia was founded on the realization that traditional, ad-hoc, experience-based methods of achieving chip design and timing closure are becoming intractable in sub-100nm geometries. Compounding the problem is the near-total lack of visibility that even the best teams have into the exact state of closure their design is in, making schedules and resource allocation hard to manage |
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PEOPLE |
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Ausdia was founded by two veteran engineers with a common desire to help solve the design closure challenge. Together, their experience runs from RTL design and verification, all the way through to implementation and post-silicon lab bringup. With more than 20 tapeouts (from 1um to 65nm) and 20 years of combined experience, the founding team has truly been exposed to the entire cycle. |
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Dr. Sam Appleton |
President, VP Engineering, Ausdia Inc
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Sam Appleton completed is B.Eng(Hons) in 1992 and received his PhD in Electronic Engineering in 1997 from the University of Adelaide, Australia.
He has held a variety of senior technical and leadership roles at SGI (Systems), Cosine Communications (Networks), and ReShape (EDA). Prior to founding Ausdia, he led the implementation of three generations of SoC MultiCore CPUs at Azul Systems.
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Atul Bhagat |
CTO, VP of Business Development, Ausdia Inc |
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Atul brings more than 11 years of technical leadership and a stellar execution track record at several Silicon Valley companies. He guides Ausdia's architectural vision and product design to align with business and market opportunity strategies. Prior to founding Ausdia, Atul was the Timing Analysis, Timing Closure, and Chip Integration technical lead at Azul Systems Inc., Reshape Inc, nVIDIA Corp., and Sun Microsystems. In this role, Atul provided technical leadership in every facet of RTL Synthesis to GDS flow/methodology development, to ensure timely and successful tapeout of highly complex chips. Atul also has extensive experience working successfully with technical, R&D teams of major EDA and IP vendors to derive optimal chip & timing closure solutions.
Atul graduated from Stanford University with a MS degree in Electrical Engineering in December 1996.
He also hold a BS in Electrical Engineering from University of Kentucky, May 1995.
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HISTORY |
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Ausdia was founded in May 2006 in a Silicon Valley garage. Thankfully, the garage is still owned by one of the founders.
A critical milestone was the establishment of a partnership with Sequence Design Inc, helping Ausdia validate the need for it’s product, as well as allowing Ausdia to leverage it’s expertise, combined with Sequence’s technology solutions, to solve critical customer problems.
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Copyright © 2007 Ausdia Inc |
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