Would you like to cut your schedule and cost by over 50%? YES - I would rather not spend days poring over 5 different tools’ check_timing reports!
Recently we worked on a chip where we started working on a fixed-cost, fixed-schedule model. The numbers are compelling – and we wanted to share them here. Now, obviously this is just one piece of the problem (it’s a big design). But we’re able to offer amazing cost & schedule advantages compared to our old way of doing things – as consultants and with a few 10000’s of lines of scriptware that came with us everywhere.
What we could offer using TimeVision Consulting on a large, complex System-On-Chip block at 65nm was….
- Block -> 30+ clocks, 500K+ instances, 121k registers
- Contents -> purchased soft & hard IP, internally-designed subsystems, ARM AMBA interfaces
- DFT – scan & bist logic inserted
- IOs – several complex & speed-sensitive IO interfaces at full-chip level
- Modes – generate all mode constraints including functional, scan shift/capture, BIST
- Requirements – IP documentation for hard/soft IP, several hours of RTL designer(s) time to discuss clocks & other design issues
- Deliverables (1) qualified & debugged constraints for synthesis and place/route, and (2) qualified, debugged & validated signoff constraints for all modes
| Task | “Typical” Consulting | TimeVision Consulting | ||
|---|---|---|---|---|
| Time Expended | Cost @$100/hr | Time Expended | FIXED cost | |
| Timing Constraint Development, Debug, Integration | 4 weeks | $16 000 | 4 days | $8 000 |
| Backend Collateral (Clock diagrams, balancing requirements, IO timing etc) | 1 week | $4 000 | 1 day | $2 000 |
| Major Iterative Respin (RTL change, new IP drop) | 2 weeks | $8 000 | 2 days | $4 000 |
| Prorated EDA tool cost | $3 000 | |||
| TOTAL TIME/COST | 7 weeks | $31 000 | 7 days | $14 000 |
Compared to what we would have done previously, we were able to deliver
- 55% cost reduction
- 5x faster turnaround time ( 4 weeks -> 4 days)
- 5x faster turnaround on iterations of the same block ( 2 weeks -> 2 days)
Our 4 day work included the review and integration of RTL desinger/IP Vendor provided point-to-point, register-level false/mcp paths and case_analysis.
Wow! Who wouldn’t want that!