• "Ausdia developed the Timing Verification and signoff environment from ground up for a highly complex, hierarchical chip project. This chip included numerous clocks, high speed interfaces, and 3rd party soft / hard IP cores from various vendors....

  Michael Raam - Sr. VP of Engineering   Mobilygen Corp (now part of Maxim)

• "Ausdia worked closely with my design team to drive several highly complex blocks through synthesis, constraints and physical implementation. They also contributed heavily to fullchip timing verification and external IP timing verification. They played a big part in the project's...

  Amal Bommireddy - VP Engineering   AMCC

• "Ausdia was brought in to help finish off some high-priority items, including chip assembly, interface timing verification and toplevel timing closure. I was impressed with their work, and thanks partly to  their efforts we taped out a 1.3B transistor chip that worked first-time ...

  John B - VP Engineering   Innovative Silicon Valley Server Startup